Generally, in the semiconductor industry the most difficulties and/or problems occur with the formation of external electrical connections and with interconnections to different components on a single substrate. Semiconductor devices are typically fabricated on a planar substrate by sequentially growing or depositing several different layers of material and then patterning or etching one or more of the layers to expose a lower surface. Metal is then deposited on the exposed surfaces for interconnections or external connections.
One problem in this process is that the etching requires masking which adds several complicated steps to the process and, consequently, a large amount of labor and cost. Also, the metal contacts require a relatively large amount of real estate and, consequently, many semiconductor devices are limited in size by the ability to provide external connections to them.
The difficulties and or problems are particularly acute when a three terminal semiconductor device is desired. The architecture of these devices is much more complicated, requiring additional masking and etching steps and a great deal more real estate is required to accommodate the extra terminal.
Accordingly, it would be highly advantageous to provide ultra-small three terminal semiconductor devices and methods of manufacture and connection.
It is another purpose of the present invention to provide novel ultra-small three terminal semiconductor devices and methods of fabrication and connection in which at least some of the interconnections are formed automatically during the formation of the various layers.
It is a further purpose of the present invention to provide novel ultra-small three terminal semiconductor devices which are smaller than previously possible with standard external terminals.
It is still a further purpose of the present invention to provide novel ultra-small three terminal semiconductor devices using simplified methods of fabrication and connection.